One way to improve the performance of large processing or telecommunications switching systems is to interconnect integrated circuits (Ics) using optics. Optically interconnecting ICs in this manner relieves the communication bottleneck that exists in such large electronic switching and computing systems by increasing the data rate for each I/O.
Hybrid CMOS silicon (Si)/gallium arsenide (GaAs) photonic chip technology has recently been developed that allows direct optical input/output from fiber bundles onto logic circuits. That photonic chip technology introduced "smart pixel" chips wherein p-i (multiple quantum well MQW!)-n modulators are used both as input detector and output device. See Goossen et al., "Demonstration of Dense Optoelectronic Integration to Si CMOS for direct Optical Interfacing of Logic Circuits to Fiber Bundles," Proc. 21st Eur. Conf. Opt. Comm. (ECOC'95 Brussels), pp. 181-188.
The aforementioned smart pixels represent an important step in the development of optoelectronic/VLSI chip technology. It would be desirable, however, to have a smart pixel utilizing different devices for detection and output. One reason for this is that such separate devices can be individually optimized for their function, i.e., input or output. In fact, such optimization may be necessary as the gate length and supply voltage of CMOS shrinks. Moreover, if separate input/output devices could be so integrated on chip, surface emitting lasers (SELs) could be introduced onto the chip. While very desirable for use as output devices, SELs do not function well as detectors, and consequently can not be used in prior art smart pixels.
The desired opto-electronic chips would thus comprise a silicon substrate that supports silicon-based electronics, with at least two different types of photonics devices, typically gallium-arsenide (GaAs) or indium-phosphide (InP)-based, disposed thereon. The different types of photonics devices would be co-located or interleaved, i.e., situated in the immediate vicinity of one another. As explained below, there have been impediments to developing opto-electronic chips having different input and output devices that are co-located.
First, there are difficulties with growing group III-V semiconductors, such as GaAs and InP, on nonpolar substrates, such as silicon. As such, if a III-V device is to be attached to a silicon substrate, such a device is grown on an appropriate substrate and then attached to the silicon. To create an opto-electronic chip having two different types of co-located III-V devices, the two devices would be typically grown on the same substrate and then attached to a silicon substrate.
Second, the photonics devices of interest, such as surface emitting lasers (SEL) and p-i-n diodes, have differing multiple epitaxial layer structures. It is not feasible, at least from a commercial point of view, to grow such dissimilarly-structured devices on a single substrate. To do so would require multiple growth steps, one for each different type of device, and further may affect device yield and performance, all of which increases manufacturing costs.
There is, therefore, a need for a commercially-viable method for attaching such differently-configured devices to a silicon substrate so that hybrid chips incorporating such devices can be produced.